EDA Workflow Orchestration: Automating RTL Verification and Synthesis with Kestra

Kestra is presented as an orchestration platform for Electronic Design Automation workflows, addressing hardware teams’ needs for large-scale parallel simulation, costly synthesis runs, artifact handling, and automated Power, Performance, and Area checks that conventional CI/CD tools may not manage effectively. In a nightly RISC-V ALU regression example, Kestra runs separate Verilator containers concurrently to test addition and subtraction operations, then invokes Yosys to synthesize the Verilog design and extract its gate count as a managed artifact. A downstream quality gate compares that count with a 500-gate area budget, causing an initial 32-bit, 903-gate design to fail before it reaches more expensive stages such as place and route. After the ALU datapath is reduced to 8 bits and its testbench updated, the same pipeline passes verification and synthesis with a 230-gate result. The approach uses version-controlled YAML flows and source files, Docker-based tools, scalable worker groups, managed artifacts, and retry mechanisms that can accommodate shared commercial EDA licenses, while remaining compatible with both open-source and command-line commercial tools.

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