Hardware-aware dynamic speculative decoding

Speculative decoding (SD) is an innovative method designed to expedite large language model (LLM) inference by proposing multiple tokens with a smaller draft model, which are then verified by a larger target model, optimizing the use of GPU resources. Traditional SD faces challenges in production environments due to dynamic batch size (BS) changes, which can render it less effective when inference becomes compute-bound. Hardware-aware dynamic speculative decoding (DSD) enhances this process by adjusting the number of draft tokens (K) based on the interaction between the model and the hardware, increasing efficiency during memory bandwidth-bound scenarios and reducing K when compute-bound. This adaptability proves advantageous across various batch sizes and model architectures, as demonstrated in benchmarks comparing vanilla, fixed-K SD, and DSD configurations. Recent contributions to vLLM incorporate DSD, ensuring compatibility with async scheduling and full CUDA Graph, thus optimizing inference efficiency and maintaining the framework's performance in dynamic environments.

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